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Tracked Chip Power in LSI Static FET Logic

IP.com Disclosure Number: IPCOM000068585D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Puri, YK [+details]

Abstract

This article describes a computer simulation technique for estimating the actual power dissipation of the logic circuit, which combines a calculation of the power distribution due to circuit component variation from chip to chip with a calculation of the power distribution due to circuit component variations within the chip.