Dual Addressable Memory
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20
The figure illustrates the data store memory (DSM) organization for a device that may have a variable feature mix requiring differing quantities of memory. As shown, chip 1 and chip Z represent memory blocks common to all models of the device. DSM chips 2 through n represent memory blocks that are present only in certain models, as a result of the presence of optional features or are currently unused address blocks to provide for future models or features. A series of chip select lines 3 are utilized by decode logic 4 to address the first address of the consecutive address block associated with the particular chip. A jumper location 6 is associated with each chip select line intermediate chip 1 select and chip Z select which can be utilized to connect the connected select line to the chip Z select line.