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The figure illustrates the use of a user-controlled memory cycle ending sequence that effectively interfaces a wide range of technologies using simple, economical circuitry.
English (United States)
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User Controlled Memory Cycle Complete Ending Sequence
The figure illustrates the use of a user-controlled memory cycle ending
sequence that effectively interfaces a wide range of technologies using simple,
Trigger 3 is the memory cycle complete circuit that signals a user that read
cycle data is valid on the data bus or that write cycle data has been written in
memory. Trigger 3 is set by the data store cycle control logic 4, and is reset by
the user dropping his memory request signal on line 5. This allows the user the
ability to adjust the length of the memory cycle complete pulse (as indicated by
the shaded areas on the memory request and memory cycle complete signal
representations) to meet the specific request. This effectively adjusts the signal
length for loading read data into buffers of any technology or circuit speed.
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