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Test Latch for Memory Timing Control

IP.com Disclosure Number: IPCOM000068613D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Nicholson, LW Pellinger, RD [+details]

Abstract

The figure illustrates a memory 3 using a request-response type interface with a number of memory users 4 (one of which is shown), implemented in field-effect transistor (FET) circuitry, and a bipolar memory controller 5. Due to substantial variations in the performance of the FET memory user, it is normally necessary to develop an elaborate clocked circuit to insure that the using device had latched-up the requested data before relinquishing control of the memory.