Browse Prior Art Database

Interval Masking of Interrupts

IP.com Disclosure Number: IPCOM000068616D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Dennison, JD Fockler, AH Goss [+details]

Abstract

In an interrupt-driven, stored program computer system, the interrupts are serviced when they occur, unless they are masked from being serviced. Such a computer system, for example, has a main program level, which executes when there are no interrupts being serviced. The lowest priority interrupt level (level 0) is used for making decisions as to which task should be performed next by the main program level. The highest priority interrupt level (level 7) handles error conditions. The other interrupt levels (levels 1-6) are assigned to handle various input/output (I/O) devices. Once the task dispatching function in interrupt level 0 has been completed, that interrupt level 16 reset, interrupts are enabled, and processing takes place in the main program level.