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Four Mask High Speed Logic Process Disclosure Number: IPCOM000068657D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

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Coady, JH [+details]


With only two chemical vapor depositions (CVD), one thermal oxide growth, and four standard photosteps, a ultra shallow junction logic field-effect transistor (FET) can be made with standard processes and tooling.