Browse Prior Art Database

Four Mask High Speed Logic Process

IP.com Disclosure Number: IPCOM000068657D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Coady, JH [+details]

Abstract

With only two chemical vapor depositions (CVD), one thermal oxide growth, and four standard photosteps, a ultra shallow junction logic field-effect transistor (FET) can be made with standard processes and tooling.