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Chip Orientor With Shrink Compensation for Gang Placement Disclosure Number: IPCOM000068696D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

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Related People

Caccoma, GA Koestner, JH O'Neill, BC Tappen, FM [+details]


This tool design is a concept adapted to fit all situations of chip gang placement where a linear shrink factor is applicable. One need only build the family of tools based on chip array and size.