Browse Prior Art Database

Chip Orientor With Shrink Compensation for Gang Placement

IP.com Disclosure Number: IPCOM000068696D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Caccoma, GA Koestner, JH O'Neill, BC Tappen, FM [+details]

Abstract

This tool design is a concept adapted to fit all situations of chip gang placement where a linear shrink factor is applicable. One need only build the family of tools based on chip array and size.