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Testable Decoder Design for Decoder Controlled Multiplexing Networks

IP.com Disclosure Number: IPCOM000068703D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Goel, P Hsieh, EP Snethen, TJ [+details]

Abstract

Problem: In data flow portions of level sensitive scan design (LSSD) logic it is common to use both the L1 and the L2 latches (of a shift register latch (SRL)) to constitute two different data registers. Suppose the two registers are multiplexed to a single output (bus, if external output) such that the multiplexor is controlled by a decoder. Then, an LSSD design rule is violated wherein the L1/L2 latches of one SRL are not allowed to feed common combinational logic. The design rule violation normally causes some faults in the decoder to be left undetected following LSSD test generation. This article introduces a decoder design practice which, when followed, guarantees that all the decoder faults will be detected in spite of the design rule violation.