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The illustrated driver circuit has improved power/performance characteristics.
English (United States)
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Memory Array Drive Circuit
The illustrated driver circuit has improved power/performance
Darlington-type memory array row drivers having a configuration illustrated
by T1 and T2 for a Row 1 driver and T3 and T4 for a Row N driver are well
known. Typically, however, resistor R1 is connected between the emitters of T1
and T2, while resistor R3 is connected between the emitters of T3 and T4.
The overall power consumption is reduced by connecting all row driver
resistors corresponding to R1 and R3 to a common reference diode voltage bias
circuit utilizing a plurality of series-connected diodes, such as D1, D2 and D3.
Such a circuit provides a better performance characteristic for the same amount
of dissipated power.
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