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Self Aligned Multiline Via Hole Disclosure Number: IPCOM000068728D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

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Heuber, K Klink, E Najmann, K Rudolph, V [+details]


In the production of LSI circuits a bundle of conductors in a first metallization plane frequently has to be connected to another bundle of conductors in a second plane through an insulation layer by way of interlevel via holes.