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Carry Save Adder Implementation Using Send Circuits

IP.com Disclosure Number: IPCOM000068759D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Shen, DT Weinberger, A [+details]

Abstract

This article describes a novel 4-2 carry-save adder, as shown in Fig. 1. It generates the lateral output carry to the next higher-order adder as a function of all 4 inputs (X2 = A1 . B1 + C1 . D1), as well as some intermediate functions (E1, F1, and G4). The intermediate functions together with the input carry from the next lower-order adder (X1) then generate the 2-bit sum S2 and S1. The lateral output carry thus removes a weight of 2 whenever the combined input weight of the "on" inputs A1 through D1 is 3 or more, and for some cases when the combined weight is 2. The remaining weight together with the lateral input carry X1 of weight 1 can have a weight of up to 3, which can be represented by S2 and S1 of weights 2 and 1, respectively.