Load Bypass for Address Arithmetic
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20
In high-performance, pipelined computers, the operand address generation process for an instruction is frequently dependent upon the results of execution of an instruction that has been decoded but not yet executed. This article describes how to reduce the degree of serialization required to preserve this dependency by optimizing for the special, but frequent, case in which the address generation is held up by a "load-type" instruction.