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Circuit 10 (Fig. 1) amplifies a difference in charge between two nodes N1 and N2.
English (United States)
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Bipolar/FET Sense Latch for Storage Array
Circuit 10 (Fig. 1) amplifies a difference in charge between two nodes N1
The emitters of bipolar transistors 11 and 12 are disconnected from ground
by a device schematically shown as a switch 13. Dual-source FET 14 is turned
on to charge N1 and N2 to the same potential, +V, and gate signal Phi1 then
clocks FET 14 off. A small charge difference from the bit lines of a storage array
or other circuit is placed on nodes N1 and N2. Switch 13 is turned on; the
positive feedback between transistors 11 and 12 greatly amplifies the small
imbalance between the two nodes. Next, FET 14 is clocked on again to latch
circuit 10. The large potential difference may now be read out from N1 and N2.
Fig. 2 is a top view of FET 14. Overlying substrate 20 is a +V supply line 21
and a gate contact 22. The two node lines 23 and 24 lie on opposite sides of
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