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Improved Test Generating D Algorithm Disclosure Number: IPCOM000068851D
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20

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Roth, JP [+details]


The D-algorithm is a method [1] widely used for computing tests for failures in acyclic logic designs. If the design is regular [2] the method naturally extends to sequential circuits. The D-algorithm is run on large designs so that its efficiency becomes of critical importance. The second version [3] of the algorithm was a substantial improvement on the first (see references). These two versions differed in the order of D-intersections, i.e., in the order of choices for extending the D-chain, a method of keeping track of the computation.