Asynchronous Failure Detection
Original Publication Date: 1978-Feb-01
Included in the Prior Art Database: 2005-Feb-20
CYCLIC TEST DETECT  is an extension of TESTDETECT for obtaining a list of all failures in a Regular Logic Design  RLD which are detected by a given test. It is widely understood that this method is much more efficient than simulation, to which it is functionally equivalent. RLD requires a certain amount of extra Logic for its implementation and for small "low-end" designs, the cost may be prohibitive. Still, for these low-end designs, tests for failures must be generated and the "coverage" of these tests determined. Indeed in the test-generating systems based, e.g., on the D-algorithm , each time a test is generated TESTDETECT or an equivalent simulation must be run, to determine failure coverage. In a Regular Logic Design no races exist to obviate the test but in a non-Regular Design this is not the case.