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Automatic Priority Interrupt Mechanism for Multiple Address Spaces Disclosure Number: IPCOM000068862D
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20

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Related People

Birney, RE Davis, MI Vergari, LP [+details]


A high-speed mechanism is provided for saving the state of a machine operating within multiple address spaces in a system, such as the IBM Series/1, which includes a central processing unit (CPU). Also, activation of an address space to handle the interrupt is included.