Browse Prior Art Database

Automatic Priority Interrupt Mechanism for Multiple Address Spaces

IP.com Disclosure Number: IPCOM000068862D
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Birney, RE Davis, MI Vergari, LP [+details]

Abstract

A high-speed mechanism is provided for saving the state of a machine operating within multiple address spaces in a system, such as the IBM Series/1, which includes a central processing unit (CPU). Also, activation of an address space to handle the interrupt is included.