Parity Checking for Multistage Counters
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20
Parity checking of count values developed by multistage LSI (large-scale integration) counting circuits is usually performed by auxiliary LSI logic circuits which predict the parity (or residue) of the next count state, generate parity (or residue) of the current count state, compare predicted and current parity factors associated with the current count state, and provide error indication when disparity is found. A problem in this respect is that the auxiliary circuits may be more extensive in size than the counting circuits which are being checked.