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Testing of LSI Logic Circuits containing "Imbedded" Shift Arrays

IP.com Disclosure Number: IPCOM000068959D
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Williams, TA [+details]

Abstract

LSI (large-scale integration) logic circuits containing "imbedded" shift arrays can be tested without direct probing connections to individual array stages. In normal "computational" mode, combinatorial logic 1 receives outputs A, B...F of shift arrays SR1 - SRN in parallel, in combination with external data inputs 3, and transfers a function of its inputs in parallel into the shift arrays.