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Trigger Stage for Integrated Synchronous Counters

IP.com Disclosure Number: IPCOM000068984D
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Jackson, JA [+details]

Abstract

Fig. 1 shows an integrated-circuit synchronous counter 1 having four trigger stages 2-5. Each stage has conventional set (S), reset (R) and clock (C) inputs, and complementary outputs (Q, Q). Trigger (T) inputs cause a stage to toggle when the C line falls, only if all T inputs are low. Such stages form a multibit counter when the Q output of each stage is tied to a T input of all following stages. Multiple counter modules may also be cascaded by introducing a ripple-carry (CRY) signal into a T input of every stage. The Q outputs of all stages together form a "down count" parallel output of counter 1, while the Q outputs are an "up count". More or fewer stages may be coupled together in the same manner.