Store Read Overrun Control
Original Publication Date: 1978-Mar-01
Included in the Prior Art Database: 2005-Feb-20
By reading contiguous bytes of data from a multichip random-access memory in which access to the random-access memory is interleaved between chips, a higher bandwidth can be obtained. Fig. 1 shows a typical chip arrangement in which the chip has a capacity of 4,096 9-bytes. It is accessed for reading in the following way. The READ LINE and a 12-BIT ADDRESS are set up to the input of the chip. ROW SELECT and COLUMN SELECT are activated so that they are co-incident for between 150 and 500 nsec. A timing mechanism with the chip is started which will ultimately latch the data byte that was accessed, this byte being available for strobing out 1.7 Mu sec after the beginning of the coincident levels of ROW and COLUMN SELECT. The access cycle can be started 2.4 Mu sec later.