Browse Prior Art Database

Vertical Chip Packaging

IP.com Disclosure Number: IPCOM000069115D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Henle, RA [+details]

Abstract

The density with which semiconductor chips can be mounted on a substrate is increased by the illustrated structures. The scheme is particularly valuable in memory chip packaging where many low power chips with low I/O requirements are to be packaged. The basic concept is to design the semiconductor chips such that the signal and power terminals are brought to one edge of the chip. The chip is then mounted vertically on a substrate which provides signal interconnection capability, power distribution to the chips, and a thermal path for conducting heat away from the chips. Since memory chips require a significantly lower number of I/O's than random logic chips, they are better suited to the vertical chip packaging concept.