Browse Prior Art Database

Skewed Loading of LSSD Shift Register Chains for Enhancing Test Generation

IP.com Disclosure Number: IPCOM000069131D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Goel, P Horstmann, PW Rosales, BC [+details]

Abstract

U.S. Patent 3,761,695 describes the level sensitive scan design (LSSD) rules and their intent. The rules disallow the L1/L2 latch of the same shift register latch (SRL) from feeding the same combinational logic function. The avowed intent of the rules is based on the test generator assuming that "only one bit of system data is contained within an SRL". Furthermore, "any violation of this rule will result in a network that will not be fully tested by test patterns generated by the test generation system". Conventional LSSD test generators are designed to treat an SRL as containing only one bit of system data.