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Test Site Failure Analysis: Two Levels of Metal for Isolation of Components

IP.com Disclosure Number: IPCOM000069156D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Scrivner, CH [+details]

Abstract

Shown in Figs. 1-3 are designs for test sites where individual components are wired at first level metal, each leading to a via hole with use of a second level metal layer to connect these via holes to large groups of devices in parallel or complete functional circuits for automated testing purposes. Isolation of components for failure analysis could then be accomplished very easily by parallel polishing to remove the second metal layer down to the via holes. Micro-probing of individual devices can be done by probing exposed metal remaining in the via holes. This approach may be applied to any test site requiring group device testing and individual device failure analysis. Example 1: Prior Test Site