Browse Prior Art Database

N Channel Master Slice

IP.com Disclosure Number: IPCOM000069181D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Kelly, GJ Wood, RA [+details]

Abstract

In some N channel FET technologies, the substrate is biased to a negative voltage, such as -5 volts. The voltage on any unconnected logical signal line, which includes diffusions, will drift toward the substrate bias voltage as the diffusion-to-substrate diode leakage charges the distributed capacitance of the signal line. Unconnected signal lines occur in master-slice designs, such as Programmed Logic Arrays, where the personality of the logic is created on a standard diffused substrate by special metallization patterns which interconnect only a portion of the diffusions to create special logic circuits.