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Circuit 10 (Fig. 1) provides very short (about 20-4O nanoseconds) time delays, which are stable and independent of temperature and supply voltage.
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High Speed Edge Triggered Timer Circuit
Circuit 10 (Fig. 1) provides very short (about 20-4O nanoseconds) time
delays, which are stable and independent of temperature and supply voltage.
Conventional emitter-coupled logic (ECL) inverter 11 transfers input voltage
Vi to ECL OR gate 12, and then on line 121, to activate timer 13, whose output
131 is fed back to OR 12 to maintain input 121 during the timeout interval
specified by external components RT and CT. Temperature-compensated
inverting driver 14 provides the overall circuit output Vo. Conventional generator
15 provides a stable reference voltage Vr on line 151 to circuits 11, 12 and 14.
Fig. 2 shows the circuit of timer unit 13. Differential pair transistors T31 and
T32 transmit the rising edge of input signal 121 via T34 to the left side of timing
capacitor CT. Since the voltage across CT cannot change instantaneously, the
emitter of T33 is pulled up beyond the bias set by R32-R34 and tracking diode
D31, thereby cutting off current flow from resistor R36 and diode D32, and
allowing the collector of 133 to approach +Vcc. CT then charges exponentially
through RT until T33 turns on again, returning the collector of T33 to its original
value of one diode drop below +Vcc.
When line 121 returns to its low state, T34 cuts off, and CT discharges
linearly through conventional current source I31. T33 also conducts this reset
current. T35 and R35 form a conventional current supply for pair T31-T32, T35
bias is also ob...