Testing the Design of Logic of a Data Processing System
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20
This article describes a method of testing the design of the logic of a data processing system. The program, RTRAN, transforms a functional specification into an equivalent logic design so that the implementation produced by a logic designer can be verified against the functional specifications by means of a comparison program. This method is much faster in terms of computer time than attempting to check the implementation by simulation. The method also checks that the implementation is a faithful reproduction of the functional specification.