Program for Physical Design Verification of FET LSI Chips
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20
This article describes an architecture and data base, which supports customized application programs and which satisfies the exacting needs of FET custom design verification. In general the physical design information is translated into an engineering description in terms of devices, nets and electrical parameters, and is retained in a master data base. Application programs for physical-to-logical checking, delay calculations, device parameter calculations, net resistance calculations, on-chip electrical circuit modelling for ASTAP, etc., can then be written to use this data base.