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Control Circuit for LSSD Testing

IP.com Disclosure Number: IPCOM000069266D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Herrell, DJ [+details]

Abstract

A circuit is disclosed whereby Level Sensitive Scan Design (LSSD) testing can be accomplished at a slower rate than that of the applied AC power. The circuit provides the necessary synchronization between LSSD and the AC power and satisfies the requirement that one and only one Functional Combinatorial Network (FCN) result is applied to a latch within one long (compared with the AC power cycle) LSSD power pulse.