Delay Measurements for High Performance Chips
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20
The disclosed method minimizes the inaccuracies caused by and/or inherent in the tester, when attempting to measure delays in the nanosecond or less range on products tested at chip level. These inaccuracies are caused by: (a) The ability of the tester to strobe data out of the unit under test exactly at a given point in time (tolerance of +.5 ns). (b) The ability of the tester to place a stimulus pulse exactly at a given point in time (tolerance of +.5 ns). (c) The effect of the test environment on the delay response of the unit under test caused by I/O probe inductance, stray capacitance and transmission line discontinuities. Method.