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Self Aligned Silicon Gate IGFET Device

IP.com Disclosure Number: IPCOM000069349D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Bhatia, HS Doney, DA Montillo, FJ [+details]

Abstract

A self-aligned silicon gate IGFET device is fabricated by a process which permits a doping level for the gate electrode different from the source and drain. The process includes the steps of: (a) thermally growing an oxide gate of the desired thickness (i.e., 200-800 Angstroms); (b) depositing polysilicon over the gate oxide while simultaneously doping the polysilicon; (c) masking the polysilicon gate electrode with, for example, photoresist or oxide; (d) ion implanting the source and drain regions with a dopant; (e) stripping the masking layer over the gate; and (f) heating to a temperature (i.e., 1100 Degrees C and steam) sufficient to drive in the dopant in the source and drain regions and to thermally grow oxide over these regions.