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Instruction Register Design with Large Scale Integrated Circuits for Reducing Data Paths

IP.com Disclosure Number: IPCOM000069360D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Angiulli, JM Garcia, LC Ling, H [+details]

Abstract

The present design decreases the data path from the I Register (instruction register) to the GPR (general register) X terminal and thereby speeds up the address generation cycle in a data processor. With reference o Fig. 1, in current data processors the GPRs are addressed by the instruction register X2 and B2 fields. In the case of an Execute instruction, the GPR X input must also be addressed using the I Register R1 field. Currently, this is accomplished by ORing the X2 and R1 fields. Unfortunately, this adds an undesirable extra level of logic in a very critical data path.