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DBI Parity Check Using DBO Echo

IP.com Disclosure Number: IPCOM000069391D
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Kiscaden, RC [+details]

Abstract

Parity checking of data on data bus in (DBI) would normally be performed by a parity checking circuit within the input/output (I/O) controller or microprocessor, but the time delays can exceed the duration of the clocking signal for gating the output of the parity check circuit. Hence, instead of using the parity check circuit within the microprocessor, the generated parity bit coming into the microprocessor is stored and then compared with the parity bit generated from the data entered into the microprocessor. If the comparison fails, a parity error has occurred. In view of the fact that the data checked is the data that has been latched in the microprocessor, the check is more complete than checking the data coming into the microprocessor.