Scheme to Minimize Timing Skews in Josephson Junction Inverter Circuits
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20
A timed inverter which is required by Josephson junction latching logic can be modified to generate the timing pulse as well as to produce the data complement. In this way, timing skews in a sequence of inverters can be minimized by regenerating the timing pulse at the time of inversion. Figs. 1-3 show a block diagram, a single turn logic (STL) embodiment and a current injection logic (CIL) embodiment.