Microinstruction Sequencing Control for Fast Signal Processing
Original Publication Date: 1978-Apr-01
Included in the Prior Art Database: 2005-Feb-20
In digital signal processing, multiplications are mostly by known constants, and they can be done by successive shifts and additions in order to save the hardware expenditure of a full-fledged high-speed multiplier. It is possible to speed up the multiplications by (a) using the "canonical signed digit code" (CSDC) representation of the constants to reduce the average number of shift-and-adds needed, (b) incorporating the CSDCs directly in multiply subroutines using one microinstruction for each shift-and-add, and (c) implementing a fast microinstruction sequencing control which is to make the to-and-fro subroutine linkages without taking extra microinstruction cycles [1, 2].