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High-speed binary look-ahead 1 (Fig. 1) uses bipolar cascode current switch logic 10 (Fig. 2), resulting in minimum power consumption and maximum speed.
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High Speed Look Ahead Carry
High-speed binary look-ahead 1 (Fig. 1) uses bipolar cascode current switch
logic 10 (Fig. 2), resulting in minimum power consumption and maximum speed.
The general Boolean expression for a carry in a look-ahead
adder is as follows: (1) Cn+1 = AnBn+Cn (An+Bn)
where An = Addend bit of nth stage
Bn = Augend bit of nth stage
Cn = Carry bit into nth stage, and
Cn+1 = Carry bit out of nth stage.
It can be shown that equation (1) can be expanded without effecting its
validity, as follows: (2) Cn+1 = CnAnBn+Cn (An+Bn) where Cn = redundant
factor, i.e., not counterpart of Cn.
Cascode logic circuit 10 (Fig. 2) implements equation (2). Referring to
circuitry 11 of circuit 10 as a CASCODE CARRY UPGRADE, look-ahead 1 (Fig. 1) is implemented with a plural number of circuits 11 stacked upon themselves as
many times as the power supply voltage will allow. Lower order Carry Input Cp
and its not counterpart Cp are provided for interconnection to a lower bit section
(not shown) when look-ahead 1 is part of a modularized system.
Look-ahead 1 provides certain advantages over conventional systems. For
example, each carry is formed with one unit of current and, hence, one unit of
power. In addition, all carries are formed simultaneously. Moreover, look-ahead
1 requires fewer devices and, hence, uses less chip area.
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