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PLA Multifunction Output Latches

IP.com Disclosure Number: IPCOM000069543D
Original Publication Date: 1978-May-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
O'Hara, AC [+details]

Abstract

In a programmable logic array (PLA) comprising an AND array 12 (Fig. 1) which drives an OR array 14, the outputs of the OR array are frequently paired such that each pair of adjacent output lines drive two inputs to a bistable circuit, such as a JK flip-flop, or a polarity hold latch using one of the lines as a gate. Other circuits, such as AND gate input latches or exclusive OR gate input latches, are also often implemented.