Adapter for Controlling LSSD Logic in a Non LSSD Environment
Original Publication Date: 1978-May-01
Included in the Prior Art Database: 2005-Feb-20
The adapter 8 (Fig. 1) concerns a large scale integration module 6 designed according to level sensitive scan design (LSSD) ground rules which dictate the existence of A-clock, B-clock and C-clock inputs, a scan input and a scan output. The adapter 8 allows the placement of LSSD module 6 in either an LSSD environment having the signals just mentioned or else in a non-LSSD environment which may, for example, have only one clock input and a reset signal for initialization along with normal data-type inputs.