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In a system wherein a series of memory cards and feature cards which include memory are utilized, it is desirable to quickly isolate an error condition to a single card that can be replaced.
English (United States)
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Parity Error Isolation to Failing Card
In a system wherein a series of memory cards and feature cards which
include memory are utilized, it is desirable to quickly isolate an error condition to
a single card that can be replaced.
As shown above, parity errors can be isolated using a single parity checking
circuit 3 which receives the data and parity bits that address memory. The output
of the parity circuit, which is indicative of an improper parity condition, sets a `D'
type flip-flop 4 to provide an output to a series of AND circuits 5 associated with
one of the various cards. Each AND 5 also receives a signal from an AND 6,
which has sufficient high-order address bits as inputs to identify the memory card
being addressed. The output of AND 5 sets a latch 7, causing a light emitting
diode (LED) 8 to be turned on and remain on until turned off by a power on reset
(POR) which resets latch 7.
Accordingly, since only a single parity checker is used, the error condition is
determined and the source isolated using a minimum of logic.
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