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Dual Processor Interface Queue

IP.com Disclosure Number: IPCOM000069586D
Original Publication Date: 1978-May-01
Included in the Prior Art Database: 2005-Feb-20

Publishing Venue

IBM

Related People

Authors:
Kaiser, JM Maher, JH [+details]

Abstract

Asynchronous information is passed between processors without an interrupt mechanism using a cyclic queue formed in storage common to both processors. This is accomplished by placing in each element of the queue listing the next queue element address and having the last element point to the first. A status byte in each element contains control information about that element, such as whether the element is full or vacant, or the content, such as type of data. If needed, a request control block (RCB) pointer is then added to point to additional data that may be passed. Two pointers are used to locate the next queue element, one for the input processor and the other for the output processor.