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A "Latch to Zero" Self Gating AND Gate

IP.com Disclosure Number: IPCOM000069641D
Original Publication Date: 1978-May-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Gheewala, TR [+details]

Abstract

The "LATCH-TO-ZERO" self-gating AND circuit, illustrated in Fig. 1, includes a flip-flop FF. As AC power is applied, currents flow into Josephson junction interferometers D1 and D2. If the stored data is a binary 1, represented by a current in the left branch of flip-flop FF, interferometer D1 switches to the voltage state, diverting current into Z1. Accordingly, current in control line portion C of device G1 is zero, G1 remains in the zero voltage state, and the current in output OL is latched to zero. On the other hand, current in control line portion T reaches its full value via unswitched interferometer D2 and switches device G2 to the voltage state, providing an output at OR.