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On Chip Testing Enhancement of a Single Chip Microprocessor

IP.com Disclosure Number: IPCOM000069657D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Leininger, JC [+details]

Abstract

0n dense large-scale integration (LSI) chips, such as microprocessor chips, obtaining adequate test coverage is often difficult or impossible due to the number of buried storage elements, such as registers, triggers, latches and sequencers. Buried storage elements do not go directly to input/output (I/O) pins, and often there is difficulty in setting them to a known state and in determining the actual state as testing progresses. In addition, large numbers of test patterns are required, which increases tester time and manufacturing expense. As an example, 100,000 test patterns may be required. Due to I/O pin limitations, it is usually not possible to add more than a small number of test points.