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Electrical Partitioning Technique to Test LSI Packages

IP.com Disclosure Number: IPCOM000069658D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Magrisso, IB Sharp, LA [+details]

Abstract

A large scale integration (LSI) test isolation technique provides improved test failure diagnosis, minimizes the number of test points required for isolation, and drastically reduces test development costs. This approach addresses the problem of generating test data for manufacturing use on LSI logic packages. The major problems in today's LSI environment are: (1) the difficulty in obtaining good testability and diagnosability and (2) the time and computer costs required for test data generation. One prior approach being used for LSI testing is the Level Sensitive Scan Design, which requires a completely synchronized design with two phase clock and constraints in the type of storage elements being used. Designs not following the above constraints require considerable effort to generate acceptable testability.