Browse Prior Art Database

Paged Storage for Central Processing Unit and Address Controls for Cycle Steal

IP.com Disclosure Number: IPCOM000069671D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Nelson, MJ [+details]

Abstract

A typical minicomputer may have predefined addressable storage, such as 64K X 18 bits, and may require more than that. A technique is described for adding electronics to the storage cards to allow for paging using an input/output (I/O) command set. With such an arrangement, cycle steal may occur to any page regardless of what page the central processing unit (CPU) is using, and provision is made for each I/O unit to have its own paging register.