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TTL Level Input Buffer for FET Circuits

IP.com Disclosure Number: IPCOM000069694D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Rose, JW [+details]

Abstract

This circuit employs positive gain capacitive feedback to generate fast, high level transitions which are synchronized to and buffered from a transistor-transistor logic (TTL) true-complement input pair of low level voltage pulses alpha and beta.