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Method to Improve Yield of Self Aligned Gate Contact in Field Effect Transistors

IP.com Disclosure Number: IPCOM000069725D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Gardiner, JR Shepard, JF Revitz, M [+details]

Abstract

The double polycrystalline silicon field-effect transistor (FET) process [*] incorporates, as a primary feature, a self-aligned gate contact-metal to polycrystalline silicon. The contact is essentially produced by covering the first polycrystalline silicon layer 10 with the silicon dioxide layer 11 and the silicon nitride layer 15 prior to gate delineation.