Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21
In the course of designing high speed logic circuits, it sometimes becomes necessary to capture and hold events of very short duration. The duration is usually so short that not more than an absolute minimum of delay can be tolerated in the feedback leg of the latching circuit. The circuit configuration to be described solves this problem by reducing the amount of delay in the feedback leg to essentially nil.