Semiconductor Chip Packaging Structure
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21
The structure shown in Figs. 1 and 2 represents a method for packaging integrated circuits to improve the thermal resistance path between the chips 1 and the cap 2 in an air-cooled environment via the use of fine thermal conductive powders 3 adequately compacted in the module cavity.