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Thermally Enhanced Semiconductor Chip Packaging Structure

IP.com Disclosure Number: IPCOM000069745D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Coughlin, CP Siwy, MJ [+details]

Abstract

This structure features the use of metal foil 1 in combination with thermal grease which enables a controllable minimum thermal grease thickness 2 at the chip interface. The metal foil 1 encapsulates a cavity of thermal media 3. A controlled volume of thermal grease is dispensed on each chip. After assembly, the cavity is pressurized, causing the foil to distend, forming the specified thermal grease interface 2 at the chip. An additional thermal enhancement is achieved through the use of studs 4 (detail A).