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A memory cell shown in the Fig. 1 circuit has a high packing density and a bipolar level performance. The memory cell may operate in either a static mode or a dynamic mode.
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High Speed, High Density Bipolar Random Access Memory
A memory cell shown in the Fig. 1 circuit has a high packing density and a
bipolar level performance. The memory cell may operate in either a static mode
or a dynamic mode.
The memory circuit consists of a PNP trsnsistor 5, NPN transistor 6, P
channel FET 7, and resistor R shown in the emitter node of PNP transistor 5.
The dotted line indicates that the substrate node of the P channel FET is the
collector of the NPN transistor 6. The resistor R may, alternatively, be put in the
emitter node of the NPN transistor 6 instead of the emitter node of the PNP
transistor 5. The R is required in a static operation, but may be avoided in a
dynamic-mode operation. Better packing density will be obtainable in dynamic
A cross-sectional view of the memory cell's physical structure is shown in
either an nepitaxial (epi) version (Fig. 2) or a p-epi version (Fig. 3). Each
memory cell is formed within a single isolated region of monocrystalline silicon.
It is preferred that the isolation be recessed silicon dioxide regions 8. The
resistor R is not shown in Figs. 2 or 3.
Typical wave forms for static-mode operation are shown in Fig. 4. In dynamic
operation the resistor R may be avoided, and the information is stored in the
floating bases of NPN and PNP transistors 6 and 5, respectively. Refreshing of
the memory is periodically required.
In dynamic-mode operation, the quiescent voltage of the sense line is about 2