Browse Prior Art Database

New Instruction and Extended Instruction Handling

IP.com Disclosure Number: IPCOM000069752D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Desautels, JC Rudy, GJ Temple, JL [+details]

Abstract

On occasion, there is the need to add new instructions or to decode instructions that are wider than the memory data path while minimizing the impact on a pre-existing processor design. The first requirement is met by extending the instruction decoder with additional decoders that respond only to respective new instructions while inhibiting the pre-existing decoders and delaying the signalling of Invalid Operation (OP). The second requirement is met by dividing a long instruction into two sequential parts and providing a "remember" register which stores only that portion of the first half which is needed to "remember" which long instruction is being executed.